In the fabrication of semiconductor integrated circuits (ICs), active device regions are formed in semiconductor substrates, isolated from adjacent devices.
Specific electrical paths connect such active devices, using high-conductivity, thin-film structures. Such structures make contacts with active devices through openings, or contact holes, in the isolating material. Of primary concern is the formation of low-resistivity contacts, in order to ensure devices perform properly. As ICs are scaled down in size, so are the devices which make up the ICs. Increases in resistance are associated with increasing circuit density and adversely affect device performance. Ways to decrease the overall resistance of ICs, including contacts, are crucial to continued successful device performance.
One way in which circuit resistance is decreased is by creating low-resistance, ohmic contacts at the device level. Ohmic contacts exhibit nearly linear current-voltage characteristics in both directions of current flow. Various factors affect the type of contact which is maintained. Increasing dopant concentration in the semiconductor contact area decreases contact resistance, up to the solubility of the dopant at the temperature at which it is introduced. Unclean semiconductor surfaces (i.e., those which contain a native oxide film) increase contact resistance. It is difficult to keep high resistance native oxides from forming due to silicon's rapid oxidation rate when exposed to an oxygen ambient.
Conventionally, ohmic contacts to semiconductor substrates are formed by the following process steps: formation of heavily doped regions where contacts are to be made; etching a contact hole in the isolating oxide layer, which covers the semiconductor substrate; cleaning the semiconductor surface to remove native oxide; depositing a metal film over the wafer by physical vapor deposition (PVD); and annealing to improve the metal-to-semiconductor contact. During the metal deposition step, obtaining good bottom step coverage is very important in maintaining the overall ohmic contact. High-aspect ratio (ratio of height-to-opening of a contact hole) holes make it even more difficult to achieve good bottom step coverage. Such holes are much deeper than they are wide, preventing good bottom step coverage by conventional process steps.
While bottom step coverage may be increased by sloping the contact hole sidewalls along the depth of the contact hole, this severely decreases achievable device density because the top of the hole is larger than normal. The type of deposition also has an effect on the resulting step coverage. Chemical vapor deposition (CVD) processes are more likely to fill high-aspect ratio holes than physical vapor deposition (PVD) processes. However, some films cannot be deposited using CVD, due to contamination introduced by CVD processes. CVD is often accompanied by a significant amount of carbon, chlorine, oxygen, and other contaminants that are detrimental to device performance. Forming films that are free from contamination is even more important as devices decrease in size. Defects resulting from such contamination are even more dominant in thinner films, which are present in smaller devices.
Different types of metal layers are used to improve ohmic contacts. The most commonly used metals are reacted with underlying silicon to form silicides. Titanium silicide is the most commonly used metal silicide due to its superior qualities, one being its ability to getter oxygen. Titanium silicide forms good ohmic contacts with both polysilicon and single-crystal silicon doped contact areas. Silicides, in general, are preferred for contact formation due to their ability to reduce native oxide remaining on semiconductor substrates. This reduction occurs after a subsequent anneal step because titanium reacts with native oxide to form titanium oxide and titanium silicide, which is highly conductive. The oxide layer remains on top of the silicide layer after annealing, separated from the underlying silicon.
A primary method for depositing films by PVD is sputtering. Sputtering is a method by which atoms on a target are displaced to a desired surface, where they form a thin film. One of the major problems associated with obtaining good bottom step coverage utilizing PVD is material "overhang" at the "shoulder" (i.e., the corner of a sidewall and the top surface) of contact openings. Material overhang, as shown at 114 and 116 of prior art FIG. 1, is formed of material deposited as layer 112 on an insulating material 122, which defines a contact hole 110 on a semiconductor substrate 124. This is a result of imperfect lines of incidence traveled by sputtered target atoms, because, in general, the ejection distribution profile of sputtered atoms is similar to a cosine profile. Thus, many sputtered atoms do not travel in a perpendicular plane, with respect to the source target surface. Doming, indicated at 126, of the sputtered material commonly occurs in the bottom of the contact hole 110 due to the imperfect lines of incidence. This results in poor bottom corner step coverage, as seen at 118 and 120, which often leads to contact failure.
Even with the use of collimated sputtering, techniques of collimating the sputtering beam are not perfect to enable precision in angles of incidence on the substrate. Many sputtered atoms do not land on the substrate at a perpendicular angle, as desired for prevention of material overhang. Thus, excess speed metal forms at the top of the opening, such that the geometry of the metallized opening does not generally match the geometry of the underlying opening in the substrate. Furthermore, prior art collimated sputtering apparatus are limited by the input power, or voltage, rewired to produce a dense plasma near the surface of the wafer. Prior art apparatus utilize a grounded collimator interposed between a target source and a substrate, which requires the use of a larger input power to produce a dense plasma at the wafer surface for depositing material within a contact hole.
Another problem is associated with the use of collimators and other traditional methods of obtaining adequate bottom step coverage. As bottom step coverage improves using traditional techniques, deposition on sidewalls of a contact hole decreases. High aspect ratio collimators essentially eliminate deposition on the sidewalls at the bottom of a contact hole. This creates a problem during subsequent process steps. The etch of a contact often trenches into the underlying substrate by hundreds of angstroms. Thus, if a barrier material is not present, subsequent metal deposition aggressively attacks the substrate, jeopardizing contact integrity. Typical barrier material comprises titanium nitride. Although titanium nitride can be deposited on sidewalls of a contact using CVD, this undesirably introduces contaminants into the titanium nitride film. Thus, there is a need for a new method for forming a barrier layer on the bottom of high aspect ratio contact sidewalls.
Thus, while a new method for forming a barrier layer is needed, it is essential that the method does not degrade the bottom step coverage of a contact hole. Maintaining adequate alloy bottom step coverage of contact holes is needed in order to decrease contact area resistance and prevent device failure. This problem is particularly acute in high-aspect ratio contact holes. There is a need for an improved method of obtaining better bottom step coverage of contact holes, without decreasing circuit density. As semiconductor chips are becoming more densely-populated with devices, it is important to decrease device resistance without severely limiting the achievable circuit density on a chip. Furthermore, prior art collimated sputtering apparatus used for practicing this invention need to be made more efficient.
Methods of removing material overhang 114 and 116, as shown in FIG. 1, at the "shoulder" of contact openings 110 and redistributing it, without simultaneously removing metal at the bottom 126 of the contact opening 110, are necessary in order to provide better step coverage. Removing material at the bottom of contact holes 110 results in unwanted junction degradation if enough material is removed. There is a further need to adapt existing equipment to accomplish better step coverage, in order to save cost and time in fabricating such devices.